PSoC6 BLE coming out of the woods
30
Sep
2017
Cypress has released more information on its PSoC6 architecture with 18 parts disclosed of which 12 support Bluetooth 4.2. Initial specs seems to indicate very good RF performance with -95dB sensitivity and 4.2/4.4 mA TX/RX current consumption for a complex Cortex-M4 + Cortex-M0+ combo. Our heavyweights SiliconLabs and Dialog are already entranched with Cortex-M4 and Cortex-M0 respectively. This is just the beginning of the battle and we expect more to jump in BT as well as Wifi to support the even increasing use cases of the IoT.
A few minor removals happened on the ATTiny10 while the new AT89LP51RB2-20AU appeared. On the Cortex-M front, the only change was the addition of the ATSAMD10D14A-MUTB5, a “B5” version of the same. It is likely a custom version.
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Microchip added close to 150 products to its portfolio, and here is the split:
- 22 (22 for LF) PIC16(L)F19155/56 with respectively 14/28 kB of Flash, 8MHz
- 16 (16) PIC16(L)F19175/76 with respectively 14/28 kB of Flash, 8MHz, about $0.15 more than 55/56, larger package, more I/O and ADC channels
- 10 (10) PIC16(L)F19185/86 with respectively 14/28 kB of Flash, 8MHz, about $0.30 more than 75/76, larger package, more I/O and ADC channels
- 50 PIC32MZ0512/1024/2028 are the high end MIPS M4K-based 200/250MHz beasts sporting respectively 512/104/2048 kB of Flash as well as Ethernet and HS USB with PHY. 1MB to 2MB price increase is ~$1 while +512kB is about $0.5, makes sense…
Interestingly, with such power, they don’t have integrated support for LCD so their competition is reduced in their target segment as long as their LCD counterparts are more expensive.
The DSPIC33 lost 16 parts while the PIC24 just 10.
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No significant changes this month at Renesas RX and RL78.
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6 months after unveiling the PSoC6 architecture, Cypress is finally releasing more open information on the family.
The PSoC 6 MCU architecture is built on a low power 40nm process, embeds a Cortex-M4 and an optional Cortex-M0+ core. Active power consumption can be as low as 22-µA/MHz (M4) and 15-µA/MHz (M0+).
The PSoC6 is comprised of 4 lines:
- PSoC60 – value line: only a 50MHz Cortex-M4 and basic CapSense with a max of 128/512kB of RAM/Flash.
- PSoC61 – programmable(?) line: boosts frequency to 150MHz and memory to 288/1024 kB of RAM/Flash with additional CapSense features, crypto acceleration and USB.
- PSoC62 – performance line: adds a 100MHz Cortex-M0+ and a full trusted execution environment. 6 parts were released.
- PSoC63 – connectivity line: add BLE including its PHY and doubles the memory footprint. 12 parts are available. If we dig deeper, it is interesting to see that the PSoC63 distinctive feature is BLE. If it can run a full BLE stack on a Cortex-M4 at 50MHz, how will the integration with the application code happen is an open question. The PSoC63 borrows lower features from the other lines, in particular:
- PSoC631: only a Cortex-M4 running at 50MHz, optional crypto, no Capsense
- PSoC633: Cortex-M4 running at 150MHz, no crypto, optional Cortex-M0+ and Capsense
- PSoC634: full house
Cypress also added 5 parts on the S6E1C32B0AGU family, but the company is pretty mum about the specs. The S6E1C332 is traditionally a Cortex-M0+ runnig at 40 MHz with 64 or 128 kB of Flash.
We’ll know more next month.
ST sprinkled changes through the portfolio including new packages to the STM32F0, STM32F3, STM32F4, STM32F7 (TFBGA). The STM32L471 got a high temp (+105C) as well.
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